Flash memory device with stable source line regardless of bit line coupling and loading effect

Abstract

A flash memory device provides for a stable source line regardless of bit line coupling during a read operation and regardless of loading effect during a manufacturing process. The flash memory device includes: a plurality of flash memory cells arranged in rows and columns, each of the flash memory cells having a control gate, a source and a drain; a plurality of first, odd-numbered word lines each of which is connected with corresponding control gate of a first set of the flash memory cells; a plurality of second, even-numbered word lines each of which is connected with corresponding control gate of a second set of the flash memory cells; a plurality of bit lines each of which is connected with corresponding a drain of the flash memory cells; and a plurality of selection transistors connected between a source line and a discharge line, the source line being connected to sources of the first and second sets of flash memory cells, the selection transistors comprising the same structure as the first and second sets of the flash memory cells.