Method and system for adjusting the step clock of a delta-sigma transformer and/or switched capacitor filter

Abstract

The invention relates to a method and system for implementing a digitally controlled sample and timing clock in a system performing analog and digital signal processing. According to the method, as the timing clock of the digital signal processing is used a clock with a controllable frequency such that said digital signal processing can have a function suited for controlling the frequency of said timing clock, and the conversion of the signal is performed in synchronism with the timing clock of the digital signal processing operation when a delta-sigma converter or a switched-capacitor filter device is employed. According to the invention, the timing and sample clocks are generated by dividing a fixed-frequency clock operating at a frequency substantially higher than that of said timing/sample clock by a digital divider of an integer division factor whose division factor is controlled by means of an at least second-order delta-sigma modulator capable of delivering an output signal of two values so that one of the modulator output signal values selects the division factor to be N while the other value selects the division factor to be N+1, and, further, the delta-sigma modulator controlling the integer-factor divider is adapted to be clocked by the timing signal generated by said integer-factor divider.