The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2005

Filed:

Oct. 09, 2003
Applicants:

Seiji Yamahira, Osaka, JP;

Norio Hattori, Kyoto, JP;

Ken Arakawa, Shiga, JP;

Inventors:

Seiji Yamahira, Osaka, JP;

Norio Hattori, Kyoto, JP;

Ken Arakawa, Shiga, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L005/00 ;
U.S. Cl.
CPC ...
Abstract

A level shift circuit realizes a high-speed and power-saved operation particularly when the input voltage is at a low level. The level shift circuit includes a first gate voltage control circuit controlled by an inverted signal of an input signal, which is inserted between a gate of a third transistor and a second output terminal; a second gate voltage control circuit controlled by the input signal, which is inserted between a gate of a fourth transistor and a first output terminal; a first transistor; and a second transistor. When the input signal shifts from 'H' to 'L', the first transistor turns OFF, the third transistor is turned ON by the first gate voltage control circuit, and then a voltage of the first output terminal rises. The second transistor turns ON, the fourth transistor is turned OFF by the second gate voltage control circuit, and the voltage of the second output terminal goes down.


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