The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2005
Filed:
Jun. 12, 2003
Dong-jun Yang, Gainesville, FL (US);
Kenneth O, Gainesville, FL (US);
Dong-Jun Yang, Gainesville, FL (US);
Kenneth O, Gainesville, FL (US);
University of Florida Research Foundation, Inc., Gainesville, FL (US);
Abstract
A high speed CMOS phase locked loop (PLL) () includes a three-state phase detection circuit having a frequency phase detector () coupled to a charge pump () for monitoring the phase differences between a reference frequency signal and a divided output frequency signal. The PLL can further include a loop filter ()coupled to the three-state phase detection circuit, a VCO () coupled to the output of the loop filter, a VCO buffer () coupled to the output of the VCO for providing an output frequency signal, and a dual modulus prescaler () having a synchronous counter (and) using feedback among D flip-flops (and) for generating the divided output frequency signal.