The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2005

Filed:

Apr. 04, 2002
Applicants:

Zhiyuan Cheng, Cambridge, MA (US);

Eugene A. Fitzgerald, Windham, NH (US);

Dimitri A. Antoniadis, Newton, MA (US);

Inventors:

Zhiyuan Cheng, Cambridge, MA (US);

Eugene A. Fitzgerald, Windham, NH (US);

Dimitri A. Antoniadis, Newton, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L029/06 ; H01L031/0328 ; H01L031/0336 ; H01L031/072 ; H01L029/04 ;
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded SiGebuffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop SiGelayer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop SiGelayer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed. The semiconductor structure includes a substrate, an insulating layer, a relaxed SiGe layer where the Ge composition is larger than approximately 15%, and a device layer selected from a group consisting of, but not limited to, strained-Si, relaxed SiGelayer, strained SGelayer, Ge, GaAs, III-V materials, and II-VI materials, where Ge compositions y and z are values between 0 and 1.


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