The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2005
Filed:
Jun. 27, 2003
Randy D. Redd, Chandler, AZ (US);
Paul A. Fisher, Tempe, AZ (US);
Olin L. Hartin, Phoenix, AZ (US);
Lawrence S. Klingbeil, Chandler, AZ (US);
Ellen Lan, Chandler, AZ (US);
Hsin-hua P. LI, Scottsdale, AZ (US);
Charles E. Weitzel, Mesa, AZ (US);
Randy D. Redd, Chandler, AZ (US);
Paul A. Fisher, Tempe, AZ (US);
Olin L. Hartin, Phoenix, AZ (US);
Lawrence S. Klingbeil, Chandler, AZ (US);
Ellen Lan, Chandler, AZ (US);
Hsin-Hua P. Li, Scottsdale, AZ (US);
Charles E. Weitzel, Mesa, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (), a first dielectric layer () above the semiconductor substrate, a first ohmic contact region () and a second ohmic contact region () above the semiconductor substrate, a gate electrode () above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate () above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer () above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer () between the gate electrode and the field plate and not located above the gate electrode or the field plate.