The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2005
Filed:
Dec. 20, 2001
Applicants:
Murari Kejariwal, Austin, TX (US);
Prasad Ammisetti, Austin, TX (US);
Axel Thomsen, Austin, TX (US);
John Laurence Melanson, Austin, TX (US);
Inventors:
Murari Kejariwal, Austin, TX (US);
Prasad Ammisetti, Austin, TX (US);
Axel Thomsen, Austin, TX (US);
John Laurence Melanson, Austin, TX (US);
Assignee:
Cirrus Logic, Inc., Austin, TX (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R031/02 ;
U.S. Cl.
CPC ...
Abstract
A method of testing an integrated circuit including the steps of observing a selected parameter at a selected test mode to detect an error. The current to the integrated circuit is stepped from a reference level by selected amount.
Kejariwal, Murari. (2005). Non-invasive, low pin count test circuits and methods (U.S. Patent No. 6937046). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6937046
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile