The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
May. 17, 2002
Jonathan Y. Chen, Yorktown Heights, NY (US);
Patrick J. Meaney, Poughkeepsie, NY (US);
William J. Scarpero, Jr., Poughkeepsie, NY (US);
Jonathan Y. Chen, Yorktown Heights, NY (US);
Patrick J. Meaney, Poughkeepsie, NY (US);
William J. Scarpero, Jr., Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of calibrating an interface is provided to automatically achieve a minimal cycle latency while maintaining synchronous data arrival between a multiplicity of self-aligning interfaces. Independent self-alignment interfaces may de-skew data bits and have them arrive on a minimum cycle boundary. However, if all the interfaces do not arrive on the same cycle, SMP designs may not function properly. For instance, with a single control chip and multiple data chips on an AMP node, the control chip often sends out controls to the dataflow chips. If the data arriving on the elastic interfaces is not synchronized with the controls, the data is not routed properly. The method employs a calibration pattern to determine the latest cycle that data is received across the elastic interfaces and calculates the target cycle for all the interfaces to match this latest cycle. The target cycle is fed back into the design and the data is received synchronously, also provided is a test to ensure that the data arrives synchronously.