The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
Oct. 03, 2003
Yuen H. Chan, Poughkeepsie, NY (US);
Louis L. Hsu, Fishkill, NY (US);
Rajiv V. Joshi, Yorktown Heights, NY (US);
Robert Chi-foon Wong, Poughkeepsie, NY (US);
Yuen H. Chan, Poughkeepsie, NY (US);
Louis L. Hsu, Fishkill, NY (US);
Rajiv V. Joshi, Yorktown Heights, NY (US);
Robert Chi-Foon Wong, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic '0' during access of the cell thereby increasing the stability of the cell, especially for cells during 'half select.' Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile