The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2005

Filed:

Sep. 03, 2003
Applicants:

Ruggero Castagnetti, Menlo Park, CA (US);

Ramnath Venkatraman, San Jose, CA (US);

Subramanian Ramesh, Cupertino, CA (US);

Inventors:

Ruggero Castagnetti, Menlo Park, CA (US);

Ramnath Venkatraman, San Jose, CA (US);

Subramanian Ramesh, Cupertino, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C005/02 ;
U.S. Cl.
CPC ...
Abstract

A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.


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