The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6933790 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 23, 2005

Filed:

Feb. 12, 2004
Applicants:

Masashi Kiyose, Gifu, JP;

Takuya Shiraishi, Higashiosaka, JP;

Inventors:

Masashi Kiyose, Gifu, JP;

Takuya Shiraishi, Higashiosaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L007/06 ;
U.S. Cl.
CPC ...
Abstract

A PLL circuit for generating a clock signal synchronized with a first reference signal generated by superimposing a wobble signal on a land pre-pit signal or a second reference signal generated from a wobble signal. The PLL circuit enables reduction in circuit scale. When a DVD-R/RW is used as an optical disc, a first loop synchronizes the frequency of a wobble signal with the frequency of a divisional clock signal, which is generated from a recording clock signal of a voltage-controlled oscillator. Further, a second loop synchronizes the phase of the divisional clock signal with the phase of the LPP signal. When a DVD+R/RW is used as an optical disc, the first loop synchronizes the frequency of the divisional clock signal with the frequency of the wobble signal. Further, the second loop applies constant voltage to a control voltage input terminal of the voltage-controlled oscillator.


Find Patent Forward Citations

Kiyose, Masashi. (2005). Phase locked loop circuit (U.S. Patent No. 6933790). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6933790

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