The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
Dec. 03, 2002
Tae-hyoung Kim, Seongnam, KR;
Yong-jin Yoon, Seoul, KR;
Nam-seog Kim, Seoul, KR;
Kwang-jin Lee, Seoul, KR;
Tae-Hyoung Kim, Seongnam, KR;
Yong-Jin Yoon, Seoul, KR;
Nam-Seog Kim, Seoul, KR;
Kwang-Jin Lee, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.