The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2005

Filed:

Nov. 20, 2003
Applicants:

Delbert R. Cecchi, Rochester, MN (US);

Michael Launsbach, Rochester, MN (US);

Curtis Walter Preuss, Rochester, MN (US);

David W. Siljenberg, Byron, MN (US);

Inventors:

Delbert R. Cecchi, Rochester, MN (US);

Michael Launsbach, Rochester, MN (US);

Curtis Walter Preuss, Rochester, MN (US);

David W. Siljenberg, Byron, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/00 ;
U.S. Cl.
CPC ...
Abstract

A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.


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