The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
Oct. 15, 2003
Jack Wong, Phoenix, AZ (US);
Sonu Daryanani, Tempe, AZ (US);
Jack Wong, Phoenix, AZ (US);
Sonu Daryanani, Tempe, AZ (US);
Microchip Technology Incorporated, Chandler, AZ (US);
Abstract
A method for integrating non-volatile memory with high-voltage and low-voltage logic in a salicide process is disclosed. The method includes forming a source region and a drain region associated with a gate region for each of a low-voltage (LV) device, a high-voltage (HV) device and a non-volatile memory (NVM) device. The HV, LV and NVM devices are electrically isolated by a field oxide region located adjacent to the respective source and drain regions. The field oxide regions are implanted with an isolation implant, such that the field implant is spaced a predetermined distance away from the HV and NVM source and drain regions. A blanking layer is deposited on the field oxide regions and a portion of the source and drain regions associated with the HV and NVM devices. Doped metal salicide regions are formed on the LV source and drain regions, all gate regions, and the exposed portions of the HV and NVM source and drain regions not covered by the blanking layer.