The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
Aug. 09, 2004
Fang-jwu Liao, Tu-chen, TW;
Wen-chun Chen, Tu-chen, TW;
Fang-Jwu Liao, Tu-chen, TW;
Wen-Chun Chen, Tu-chen, TW;
Hon Hai Precision Ind. Co., Ltd., Taipei Hsien, TW;
Abstract
A land grid array connector () for electrically connecting a CPU package () to a printed circuit board includes a housing () and a number of contacts received in passageways () of the housing. The housing has a bottom wall () and sidewalls (). The bottom wall and the sidewalls cooperatively define a receiving space () for accommodating the package therein. Protrusion member () is formed on the sidewalls and extends inwardly into the receiving space. A through hole () below the protrusion member is defined in the bottom wall for facilitating molding the protrusion member. The protrusion member is configured with a vertical abutting surface () formed at a lateral end toward the receiving space thereof. The bottom wall forms a mounting surface () for sustaining the CPU chip thereon. A vertical shortest distance is formed between a lowest end of the abutting surface of the protrusion member and the mounting surface of the bottom wall. This configuration can protect the sidewalls of the housing from being scraped during insertion of the package into the housing. Reliable electrical connection between the package and contacts of the land grid array connector is secured.