The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2005

Filed:

May. 15, 2002
Applicants:

Miodrag Potkonjak, Freemont, CA (US);

Seapahn Megerian, West Hills, CA (US);

Advait Mogre, Sunnyvale, CA (US);

Dusan Petronavic, Cupertino, CA (US);

Inventors:

Miodrag Potkonjak, Freemont, CA (US);

Seapahn Megerian, West Hills, CA (US);

Advait Mogre, Sunnyvale, CA (US);

Dusan Petronavic, Cupertino, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F017/50 ;
U.S. Cl.
CPC ...
Abstract

A method for optimizing an algorithm specified for implementation on an integrated circuit for a specified application. The algorithm is analyzed with respect to its performance, and estimates of implementation area and speed are calculated. Specifically, the degrees of freedom for the algorithm alternations under specific targeted implementation objective functions and constraints are identified. The algorithm solution space is then searched to identify the algorithm structure that is best suited for the specified design goals and constraints. Algorithm parameters which satisfy performance metrics and can be implemented with minimum silicon area are identified.


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