The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2005

Filed:

Oct. 29, 2002
Applicants:

Jason R. Gunderson, Fort Collins, CO (US);

Jonathan E. Lachman, Fort Collins, CO (US);

Robert Mcfarland, Murphy, TX (US);

Inventors:

Jason R. Gunderson, Fort Collins, CO (US);

Jonathan E. Lachman, Fort Collins, CO (US);

Robert McFarland, Murphy, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F017/50 ; H03K019/00 ;
U.S. Cl.
CPC ...
Abstract

A system and method is disclosed for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group.


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