The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2005
Filed:
Jul. 15, 2003
Kyu-chan Lee, Seoul, KR;
Sang-jae Rhee, Kyunggi-do, KR;
Jung-yong Choi, Kyunggi-do, KR;
Jong-hyun Choi, Kyunggi-do, KR;
Jong-sik NA, Kyunggi-do, KR;
Jae-hoon Kim, Kyunggi-do, KR;
Kyu-Chan Lee, Seoul, KR;
Sang-Jae Rhee, Kyunggi-do, KR;
Jung-Yong Choi, Kyunggi-do, KR;
Jong-Hyun Choi, Kyunggi-do, KR;
Jong-Sik Na, Kyunggi-do, KR;
Jae-Hoon Kim, Kyunggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.