The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2005

Filed:

Jun. 26, 1997
Applicants:

Raj Ramanujan, Leominster, MA (US);

James B. Keller, Arlington, MA (US);

William A. Samaras, Haverhill, MA (US);

John Derosa, Princeton, MA (US);

Robert E. Stewart, Stow, MA (US);

Inventors:

Raj Ramanujan, Leominster, MA (US);

James B. Keller, Arlington, MA (US);

William A. Samaras, Haverhill, MA (US);

John Derosa, Princeton, MA (US);

Robert E. Stewart, Stow, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F013/14 ; G06F013/36 ;
U.S. Cl.
CPC ...
Abstract

A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.


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