Segmented, current-mode digital-to-analog converter

Abstract

A segmented current mode DAC () is disclosed herein having a current matching circuit () that compensates for the current mismatch produced by the transistors of each current source. This segmented current mode DAC () includes an input stage (), a first and second controllable current source (), a current matching circuit (), and an output switching network (). The first controllable current source () couples to receive a mirrored current as provided by the input stage () to provide a current source output controllable in current increments responsive to the M least significant bits for converting of the digital signal to analog form, where M is less than N. The second controllable current source () couples to receive the mirrored current to provide a current source output controllable in current increments responsive to the N−M most significant bits for converting of the digital signal to analog form. The current matching circuit () couple between the first and second controllable current sources () to match the current of the first controllable current source () and the second controllable current source (). Specifically, the current matching circuit () connects between each sub-DAC () to force the drain-to-source voltage of a transistor () representing the first bit of the MSB binary weighted sub-DAC () to be the same as the drain-to-source voltage of the transistor () representing the LSB thermometer decoded sub-DAC ().