Variable modulus interpolator, and a variable frequency synthesizer incorporating the variable modulus interpolator

Abstract

A variable modulus interpolator () for interpolating a fractional partof a rational number by which a reference frequency is to be divided in a multi-divisor divider in a variable frequency synthesizer comprises a third order sigma-delta modulator () of MASH cascade configuration having first, second and third sigma-delta stages (). The numerator F of the fraction is selectable and is inputted to a first register () for inputting to the input of the first sigma-delta stage () of the sigma-delta modulator (). The denominator M of the fraction is selectable and is inputted to a second register. A single bit output quantiser () in each sigma-delta stage () outputs a sign bit indicative of the sign of the output from an integrator () in the corresponding sigma-delta stage (). A multiplier () is located in the negative feedback loop of each sigma-delta modulator for multiplying the output of the quantiser () being fed back by the denominator M stored in the second register (). The negative of the fed back product of the multiplier and the quantiser output is summed in a first summer () in the corresponding sigma-delta stage () with the input to that stage, and is applied to the integrator (). Quantiser noise from the first and second stages () form the input to the first summers () of the second and third sigma-delta stages (). The outputs of the respective sigma-delta stages () are summed together in an intermediate summer () and in a main summer () to provide a varying digital code for applying to a control input of a multi-divisor divider for providing varying values of divisors for fractional division. The variable modulus interpolator () is particularly suitable for use in conjunction with an indirect frequency synthesizer, and by varying the value of the denominator M the frequency step size between selectable frequencies can be varied.