The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2005
Filed:
Oct. 31, 2003
Shiu Chung Ho, Essex Junction, VT (US);
Ivan L. Wemple, Shelburne, VT (US);
Stephen D. Wyatt, Jericho, VT (US);
Shiu Chung Ho, Essex Junction, VT (US);
Ivan L. Wemple, Shelburne, VT (US);
Stephen D. Wyatt, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit designed to reduce on-chip noise coupling. In one embodiment, circuit () includes the following: a circuit transformer () capable of converting a noise sensitive input reference clock signal to an output signal having a voltage compatible with a predetermined sink voltage logic level; and a biased receiver network () having a PFET current mirror () coupled with a NFET current (), the biased receiver transistor network designed to multiply the transformer signal to offset a mutual coupling loss of the transformer. In at least one alternative embodiment, the input reference clock signal originates at an off-chip clock generator circuit () and the output signal from receiver () is input to a PLL (). In another alternative embodiment, the transformer is a monolithic integrated transformer. Another alternative embodiment of the present invention is a method of reducing on-chip noise coupling.