The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2005
Filed:
Nov. 21, 2002
Guu Lin, San Jose, CA (US);
Stephanie Tran, San Jose, CA (US);
Bruce Pederson, San Jose, CA (US);
Brad Vest, San Jose, CA (US);
Jim Park, San Jose, CA (US);
Jay Schleicher, Santa Clara, CA (US);
Guu Lin, San Jose, CA (US);
Stephanie Tran, San Jose, CA (US);
Bruce Pederson, San Jose, CA (US);
Brad Vest, San Jose, CA (US);
Jim Park, San Jose, CA (US);
Jay Schleicher, Santa Clara, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.