The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2005
Filed:
Feb. 18, 2003
Steven M. Leibiger, Falmouth, ME (US);
Ronald B. Hulfachor, Cape Elizabeth, ME (US);
Michael Harley-stead, Portland, ME (US);
Daniel J. Hahn, Portland, ME (US);
Steven M. Leibiger, Falmouth, ME (US);
Ronald B. Hulfachor, Cape Elizabeth, ME (US);
Michael Harley-Stead, Portland, ME (US);
Daniel J. Hahn, Portland, ME (US);
Fairchild Semiconductor Corporation, South Portland, ME (US);
Abstract
A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.