The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2005

Filed:

May. 30, 2002
Applicants:

Jung-woo Park, Seoul, KR;

Jung-min Ha, Seoul, KR;

Inventors:

Jung-Woo Park, Seoul, KR;

Jung-Min Ha, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L027/108 ; H01L029/76 ; H01L029/94 ; H01L031/119 ;
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium single crystalline layer or a dual layer in which a silicon-germanium single crystalline layer covers a silicon single crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium single crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a single crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium single crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium single crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode. After forming the silicon germanium single crystalline layer to a predefined thickness, a silicon single crystalline layer can be further grown at the silicon germanium single crystalline layer. After forming the silicon germanium single crystalline layer and before forming the dielectric layer, annealing can be performed for a predefined time.


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