The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2005

Filed:

Sep. 05, 2001
Applicants:

Jung-wook Shin, Seoul, KR;

Jae-seung Kim, Seoul, KR;

Hong-seub Kim, Seoul, KR;

Inventors:

Jung-Wook Shin, Seoul, KR;

Jae-Seung Kim, Seoul, KR;

Hong-Seub Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/336 ; H01L021/425 ;
U.S. Cl.
CPC ...
Abstract

A memory comprises a gate oxide layer formed on a semiconductor substrate; an ion trap region formed in a corner portion of the gate oxide layer; a floating gate formed on the gate oxide layer; a dielectric layer formed on the floating gate; a control gate formed on the dielectric layer; a spacer provided along side walls of a formed gate; an LDD formed under the spacer on the semiconductor substrate, the LDD being doped at a low concentration with impurities; and a source/drain region formed on an element region of the semiconductor substrate contacting the LDD, the source/drain region being doped at a high concentration with impurities. In one embodiment, the ion trap region is formed by performing ion injection into a corner portion of the gate oxide after the gate, including the control gate and the floating gate, is formed.


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