The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2005
Filed:
Oct. 21, 2003
Osamu Ogawa, Neyagawa, JP;
Dai Hattori, Otsu, JP;
Keiichi Kurokawa, Takarazuka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A high-level synthesis method of the present invention includes: generating a CDFG (Control Data Flow Graph) based an input file describing a behavior of a digital circuit; allocating each node of the CDFG generated in the CDFG generation, expressing contents of processing, to a time synchronized with a clock called a Step, based on the CDFG and a constraint condition of the digital circuit described in a constraint file, thereby scheduling the CDFG; generating allocation information representing how resources for constituting the digital circuit are allocated to respective nodes of the CDFG scheduled in the scheduling, based on resource-level layout information representing a layout of the resources, and circuit information representing a connecting relationship between the resources; and outputting the circuit information generated in the allocation and circuit information generation.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile