The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2005
Filed:
Oct. 31, 2003
Luiz A. Barroso, Mountain View, CA (US);
Kourosh Gharachorloo, Menlo Park, CA (US);
Andreas Nowatzyk, San Jose, CA (US);
Mosur K. Ravishankar, Mountain View, CA (US);
Robert J. Stets, Jr., Palo Alto, CA (US);
Luiz A. Barroso, Mountain View, CA (US);
Kourosh Gharachorloo, Menlo Park, CA (US);
Andreas Nowatzyk, San Jose, CA (US);
Mosur K. Ravishankar, Mountain View, CA (US);
Robert J. Stets, Jr., Palo Alto, CA (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.