The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2005

Filed:

Sep. 25, 2001
Applicants:

Zheng Chen, Colorado Springs, CO (US);

Vikram Joshi, Colorado Springs, CO (US);

Myoungho Lim, Colorado Springs, CO (US);

Carlos A. Paz DE Araujo, Colorado Springs, CO (US);

Larry D. Mcmillan, Colorado Springs, CO (US);

Yoshihisa Kato, Shiga, JP;

Tatsuo Otsuki, Osaka, JP;

Yasuhiro Shimada, Kyoto, JP;

Inventors:

Zheng Chen, Colorado Springs, CO (US);

Vikram Joshi, Colorado Springs, CO (US);

Myoungho Lim, Colorado Springs, CO (US);

Carlos A. Paz de Araujo, Colorado Springs, CO (US);

Larry D. McMillan, Colorado Springs, CO (US);

Yoshihisa Kato, Shiga, JP;

Tatsuo Otsuki, Osaka, JP;

Yasuhiro Shimada, Kyoto, JP;

Assignees:

Symetrix Corporation, Colorado Springs, CO (US);

Matsushita Electric Industrial Co., Ltd., Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C011/22 ;
U.S. Cl.
CPC ...
Abstract

A ferroelectric memoryincludes a group of memory cells (), each cell having a ferroelectric memory element (etc.), a drive line (etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (etc.) between the memory cells and the bit line, a set switch (etc.) connected between the drive line and the memory cells, and a reset switch (etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.


Find Patent Forward Citations

Loading…