The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2005
Filed:
Jun. 14, 2001
Lior Amarilio, Kiryat Ala, IL;
Ariela Benasus, Haifa, IL;
Michael Barshay, Nesher, IL;
Tomer Refael Ben-chen, Binyamina, IL;
Lior Amarilio, Kiryat Ala, IL;
Ariela Benasus, Haifa, IL;
Michael Barshay, Nesher, IL;
Tomer Refael Ben-Chen, Binyamina, IL;
Chip Express (Israel) Ltd., Haifa, IL;
Abstract
This invention discloses a cell forming part of a customizable logic array device, the cell including at least first () and second multiplexers, each having a select input and an output, at least two inverters (), each having an input and an output, and electrical connections (), selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the at least two inverters. A customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers is also disclosed. The invention additionally discloses a cell forming part of a customizable logic array device, the cell including a pair of identical logic portion located on opposite sides of a driver portion. The driver portion includes at least two drivers, each having an input and an output. The pair of identical logic portions including at least one multiplexer () having a select input and an output, at least one inverter () having an input and an output and at least one NAND gate () having two inputs and an output. Preferably the cell also includes electrical connections, selectably connecting each output of each element of the cell to any other input or output of any other element of the same cell, preferably at the same metal layer.