The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2005
Filed:
Oct. 22, 2002
Applicant:
Hiroshi Ohara, Shiojiri, JP;
Inventor:
Hiroshi Ohara, Shiojiri, JP;
Assignee:
Seiko Epson Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L023/48 ; H01L023/52 ; H01L029/40 ;
U.S. Cl.
CPC ...
Abstract
An integrated circuit is electrically connected with a plurality of pads. A passivation film covers a part of each of the pads and exposes the other part of each of the pads. Bumps are formed on the pads, respectively. Each of the bumps is a single layer disposed on a part of each of the pads exposed from the passivation film, and on the passivation film.
Ohara, Hiroshi. (2005). Semiconductor chip and wiring board with bumps formed on pads/land and on passivation/insulation film and manufacturing method of the same (U.S. Patent No. 6924553). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6924553
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile