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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6924525 B1

PDFFull Text
Date of Patent:
Aug. 02, 2005

Filed:

Aug. 19, 2003

Semiconductor integrated circuit device including memory cell section having capacitor over bitline structure and with the memory and peripheral sections having contact plug structures containing a barrier film and effecting electrical contact with misfets of both memory and peripheral sections

Applicants:

Seiji Narui, Hamura, JP;

Tetsu Udagawa, Iruma, JP;

Kazuhiko Kajigaya, Iruma, JP;

Makoto Yoshida, Ome, JP;

Inventors:

Seiji Narui, Hamura, JP;

Tetsu Udagawa, Iruma, JP;

Kazuhiko Kajigaya, Iruma, JP;

Makoto Yoshida, Ome, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:

Antonelli, Terry, Stout & Kraus, LLP

Primary Examiner:

Nathan J Flynn

Assistant Examiner:

Kevin Quinto

Int. Cl.
CPC ...
H01L027/108 ;
U.S. Cl.
CPC ...
Abstract

The sheet resistance of a gate electrodeA (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL, BLare, respectively, 2 Ω/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrodeA (the word line WL) or the bit lines BL, BLby which the number of the steps of manufacturing the DRAM can be reduced.

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Narui, Seiji. (2005). Semiconductor integrated circuit device including memory cell section having capacitor over bitline structure and with the memory and peripheral sections having contact plug structures containing a barrier film and effecting electrical contact with misfets of both memory and peripheral sections (U.S. Patent No. 6924525). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6924525

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