The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2005
Filed:
Jan. 22, 2004
Sang-hun OH, Gumi-si, KR;
Yong-min Ha, Gumi-si, KR;
Jae-deok Park, Gumi-si, KR;
LG.Philips LCD Co., Ltd., Seoul, KR;
Abstract
An array substrate for use in a liquid crystal display device is fabricated by the steps of forming a buffer layer on a substrate; forming a polycrystalline-silicon active layer on the buffer layer, the said active layer having an island shape; forming a gate insulation layer on the buffer layer to cover the polycrystalline-silicon active layer; forming a first metal layer on the gate insulation layer; forming a second metal layer on the first metal layer; patterning the first and second metal layer to form a gate electrode, a gate line and a gate shorting bar; forming a source contact area and a drain contact area at both sides of the polycrystalline-silicon active layer; forming an interlayer insulator on the gate insulation layer to cover the patterned first and second metal layers; patterning the interlayer insulator and the gate insulation layer so as to form a first contact hole to the source contact area and the second contact hole to a drain contact area, patterning a portion of the interlayer insulator on the gate shorting bar so as to form an etching hole, eliminating a portion of the first layer of the gate insulation layer under the etching hole, and forming a bridge portion in the second layer of the gate insulation layer under the etching hole; forming a third metal layer on the gate insulation layer and on the bridge portion; patterning the third metal layer so as to form a source electrode and a drain electrode, and removing the bridge portion when patterning the third metal layer; and forming a passivation layer on the interlayer insulator and on the patterned third metal layer.