The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2005

Filed:

Apr. 04, 2001
Applicant:

Hiroki Koike, Tokyo, JP;

Inventor:

Hiroki Koike, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C029/00 ; G11C016/00 ;
U.S. Cl.
CPC ...
Abstract

The object of the present invention is to provide a semiconductor memory device wherein analog data signal potential read out from a memory cell to bit-line (bit-line read-out potential) can be measured precisely. In this invention, a sense part circuit blockdifferentially amplifies data signal occurring on one of a pair of bit-lines (for example, bit-line BLNk, BLTk) in a memory cell array, and reference signal occurring on another of the pair, and data is read out. Bit-lines BLN, BLT, -, BLNn, BLTn are connected to a reference potential setup circuit block. Reference potential setup circuitsets up potential assigned from outside of the device as potential of reference signal on bit-line. Bit-line read-out potential is indirectly obtained from the differential amplification result by controlling the reference potential with the reference potential setup circuit block


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