The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2005
Filed:
May. 20, 2004
Shinichi Fukada, Tokyo, JP;
Shinichi Fukada, Tokyo, JP;
Seiko Epson Corporation, Tokyo, JP;
Abstract
The invention provides a semiconductor device and a method for manufacturing the same that are capable of contributing to a further chip downsizing in the cross-point FeRAM. More particularly, a first local wiring can be formed on a first interlayer insulating layer so as to connect a drain region and part of a gate electrode in a MOS transistor and a top layer wiring. A second local wiring can be formed on a second interlayer insulating layer so as to connect a source region in the MOS transistor and a lower electrode layer in a ferroelectric capacitor, and further to connect part of a gate electrode in the MOS transistor and the top layer wiring. The MOS transistor that makes up of a peripheral circuitry using only the first and second local wiring can be formed directly under a capacitor array forming region of cross-point FeRAM.