The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2005
Filed:
May. 10, 2000
Bruce Leroy Beukema, Hayfield, MN (US);
Timothy Carl Bronson, Vestal, NY (US);
Ronald Edward Fuhs, Rochester, MN (US);
Glenn David Gilda, Binghamton, NY (US);
Anthony J Bybell, Carrboro, NC (US);
Stefan Peter Jackowski, Endicott, NY (US);
William Garrett Verdoorn, Jr., Rochester, MN (US);
Phillip G Williams, Owego, NY (US);
Bruce Leroy Beukema, Hayfield, MN (US);
Timothy Carl Bronson, Vestal, NY (US);
Ronald Edward Fuhs, Rochester, MN (US);
Glenn David Gilda, Binghamton, NY (US);
Anthony J Bybell, Carrboro, NC (US);
Stefan Peter Jackowski, Endicott, NY (US);
William Garrett Verdoorn, Jr., Rochester, MN (US);
Phillip G Williams, Owego, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.