The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2005
Filed:
Sep. 04, 2003
Applicant:
Regan N. Mills, Stoneham, MA (US);
Inventor:
Regan N. Mills, Stoneham, MA (US);
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M001/06 ; H03M001/66 ;
U.S. Cl.
CPC ...
Abstract
A parallel DAC topology reduces systematic linearity errors by offsetting the digital codes inputted to the individual DACs from one another. Linearity errors that would normally add together are thus reduced.
Quick Actions:
Mills, Regan. (2005). Parallel converter topology for reducing non-linearity errors (U.S. Patent No. 6919833). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6919833
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile