Methods to control the droop when powering dual mode processors and associated circuits

Abstract

A DC/DC converterhas a DACthat receives a code associated with desired processor operating voltage and sets the reference voltage on its output. The reference voltage (V) is boosted by the buffer amplifierto center the droop along the median load. A sensed current signal Iis proportional to the load current Iand can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain G. A droop control feedback circuit includes an error amplifier. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency Fand transformed to the current Ithat creates the voltage drop across the resistor R. The other input is coupled to the buffer amplifier output. As a result, the output voltage of the converteris inversely proportionally to the load current and is invariant to the processor clock frequency changes associated with the processor mode switchover. Other embodiments modify the gain of the error amplifier, or offset the gain and hold the amount of droop constant.