Structure of a capacitive element of a booster circuit included in a semiconductor device and method of manufacturing such a structure

Abstract

A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.