The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2005

Filed:

Dec. 23, 2002
Applicants:

Russell J. Henry, Wichita, KS (US);

Bret S. Weber, Wichita, KS (US);

Dennis E. Gates, Wichita, KS (US);

John R. Kloeppner, Buhler, KS (US);

Keith W. Holt, Wichita, KS (US);

Inventors:

Russell J. Henry, Wichita, KS (US);

Bret S. Weber, Wichita, KS (US);

Dennis E. Gates, Wichita, KS (US);

John R. Kloeppner, Buhler, KS (US);

Keith W. Holt, Wichita, KS (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F003/00 ;
U.S. Cl.
CPC ...
Abstract

Methods and associated structure for improving storage system performance by reducing latency associated with communication medium transactions internal to a storage subsystem. In one aspect of the present invention, an I/O control element associated with a storage system transmits prefetch read requests to an associated storage element of the storage system in response to receipt of a host system request. This allows the storage element to commence data transfer to the I/O element in advance of the I/O element returning the data to the host system. Subsequent transfers of data from the storage element to the I/O element then overlap the transfer of data from the I/O element to the host. In another specific aspect of the present invention, methods and associated structures eliminate latency associated with PCI-X bus split transactions between the front-end (host interface portion) of the I/O element and the back-end (storage element interface) of the I/O element by overlapping the transfer of prefetched data to the host system with continued fetching of subsequent data from the storage element.


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