The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2005

Filed:

Jun. 06, 2002
Applicants:

William Paul Mazotti, San Martin, CA (US);

Peter Deane, Los Altos, CA (US);

Luu Thanh Nguyen, Sunnyvale, CA (US);

Ken Pham, San Jose, CA (US);

Bruce Carlton Roberts, San Jose, CA (US);

Jia Liu, San Jose, CA (US);

Yongseon Koh, Sunnyvale, CA (US);

John P. Briant, Cambridge, GB;

Roger William Clarke, Cambridge, GB;

Michael R. Nelson, Cambridge, GB;

Christopher J. Smith, Swaffham Prior, GB;

Janet E. Townsend, Fulbourn, GB;

Inventors:

William Paul Mazotti, San Martin, CA (US);

Peter Deane, Los Altos, CA (US);

Luu Thanh Nguyen, Sunnyvale, CA (US);

Ken Pham, San Jose, CA (US);

Bruce Carlton Roberts, San Jose, CA (US);

Jia Liu, San Jose, CA (US);

Yongseon Koh, Sunnyvale, CA (US);

John P. Briant, Cambridge, GB;

Roger William Clarke, Cambridge, GB;

Michael R. Nelson, Cambridge, GB;

Christopher J. Smith, Swaffham Prior, GB;

Janet E. Townsend, Fulbourn, GB;

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L023/12 ; H01L023/28 ;
U.S. Cl.
CPC ...
Abstract

Concepts for conveniently arranging devices for the transduction of signals to and from voltage and current domains to infrared radiation domains is described. Specifically, optoelectronic components and methods of making the same are described. In one aspect, the optoelectronic component includes a base substrate having a pair of angled (or substantially perpendicular) faces with electrical traces extending therebetween. A semiconductor chip assembly is mounted on the first face of the base substrate and a photonic device is mounted on the second face. Both the semiconductor chip assembly and the photonic device are electrically connected to traces on the base substrate. The semiconductor chip assembly is generally arranged to be electrically connected to external devices. The photonic devices are generally arranged to optically communicate with one or more optical fibers. The described structure may be used with a wide variety of photonic devices. In some embodiments the base substrate is formed from a ceramic material having the electrical traces formed thereon. In other implementations the substrate includes a backing block having a flexible printed circuit substrate adhered thereto.


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