The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6915942 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 12, 2005

Filed:

May. 29, 2002
Applicants:

Shinji Watanabe, Tokyo, JP;

Hiroshi Sakai, Tokyo, JP;

Motoji Suzuki, Tokyo, JP;

Makoto Igarashi, Niigata, JP;

Akihiro Tanaka, Niigata, JP;

Inventors:

Shinji Watanabe, Tokyo, JP;

Hiroshi Sakai, Tokyo, JP;

Motoji Suzuki, Tokyo, JP;

Makoto Igarashi, Niigata, JP;

Akihiro Tanaka, Niigata, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B23K031/02 ;
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a mount structure according to the present invention which forcedly cools down a melted solder paste on a printed circuit board at a cooling speed of 1.5° C./second or higher to solidify the solder paste when an electronic part is mounted on the printed circuit board by reflow processing.


Find Patent Forward Citations

Watanabe, Shinji. (2005). Method of manufacturing mount structure without introducing degraded bonding strength of electronic parts due to segregation of low-strength/low-melting point alloy (U.S. Patent No. 6915942). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6915942

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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