The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2005
Filed:
Dec. 21, 2001
Mauricio Calle, Austin, TX (US);
Joel R. Davidson, Austin, TX (US);
James T. Kirk, Austin, TX (US);
Betty A. Mcdaniel, Austin, TX (US);
Maurice A. Uebelhor, East Leander, TX (US);
Mauricio Calle, Austin, TX (US);
Joel R. Davidson, Austin, TX (US);
James T. Kirk, Austin, TX (US);
Betty A. McDaniel, Austin, TX (US);
Maurice A. Uebelhor, East Leander, TX (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
A network processor or other type of processor includes first classification circuitry, scheduling circuitry and second classification circuitry. The first classification circuitry is configured to determine for a given packet received by the processor whether the packet has one or more errors. The scheduling circuitry in an illustrative embodiment receives an indication of the error determination made by the first classification circuitry, and based on the indication controls the dropping of the given packet from the processor memories if the packet has one or more errors, e.g., via a flush transmit command. The second classification circuitry, which may be implemented as a single classification engine or a set of such engines, may be configured to perform at least one classification operation for the given packet, e.g., if the packet is supplied thereto by the scheduling circuitry.