Controllable delay circuit for delaying an electrical signal

Abstract

The invention relates to a controllable delay circuit for delaying an electrical input signal wherein the controllable delay circuit is arranged for receiving an input signal and at least one control signal, wherein, in use, the delay circuit delays the input signal by a delay for generating an output signal, wherein the delay is a function of the at least one control signal, wherein the delay circuit comprises a first module for generating a base signal and at least one support signal on the basis of the input signal and the at least one control signal, wherein, in use, the phase and/or the amplitude of the at least one support signal is controllable with respect to the phase and/or the amplitude of the base-signal by means of the at least one control signal, wherein the delay circuit also comprises a second module connected to the first module, which second module comprises a signal-conductor and at least one support conductor, wherein the signal conductor and the at least one support conductor extend, at least over a part of the conductors, essentially parallel to one another in one another's vicinity, wherein, in use, the first module supplies the base signal to a first end of the signal conductor for generating an output-signal at a second end of the signal conductor, and wherein, in use, the first module supplies the at least one support signal to the at least one support conductor.