The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6913989 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 05, 2005

Filed:

Jan. 06, 2004
Applicant:

Hiroshi Takenaka, Kyoto, JP;

Inventor:

Hiroshi Takenaka, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/44 ; G03C005/00 ; G03C005/04 ;
U.S. Cl.
CPC ...
Abstract

In a semiconductor integrated circuit device including a plurality of semiconductor devices formed on a substrate, the principal plane of the substrate is partitioned into a plurality of device regions and into a plurality of routing regions each crossing a boundary between the plural device regions. A device group including one or more semiconductor devices among the plural semiconductor devices and a local interconnect for connecting the semiconductor devices included in the device group are disposed within the plural device regions. A global routing for connecting the device groups to each other is disposed within each of the plural routing regions.


Find Patent Forward Citations

Takenaka, Hiroshi. (2005). Method of exposing a semiconductor integrated circuit including device regions and global routing region (U.S. Patent No. 6913989). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6913989

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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