The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2005
Filed:
Apr. 30, 2003
Young-sub You, Gyeonggi-do, KR;
Hyeon-deok Lee, Seoul, KR;
Tae-soo Park, Gyeonggi-do, KR;
Heon-heoung Leam, Seoul, KR;
Bong-hyun Kim, Incheon, KR;
Yong-woo Hyung, Kyeonggi-do, KR;
Young-Sub You, Gyeonggi-do, KR;
Hyeon-Deok Lee, Seoul, KR;
Tae-Soo Park, Gyeonggi-do, KR;
Heon-Heoung Leam, Seoul, KR;
Bong-Hyun Kim, Incheon, KR;
Yong-Woo Hyung, Kyeonggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.