The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2005

Filed:

Nov. 20, 2003
Applicants:

Se-jun Kim, Seoul, KR;

Seung-ryul Park, Incheon-kwangyokshi, KR;

Inventors:

Se-Jun Kim, Seoul, KR;

Seung-Ryul Park, Incheon-kwangyokshi, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F001/1335 ;
U.S. Cl.
CPC ...
Abstract

An array substrate of a liquid crystal display device having a thin film transistor on a color filter structure and a method of fabricating the same are disclosed in the present invention. The liquid crystal display device having a thin film transistor on color filter structure array substrate includes a gate line and a gate electrode on a substrate, the gate line and the gate electrode being formed of a light-shielding material, a color filter layer on the substrate, covering edge portions of the gate line and the gate electrode, an overcoat layer over the substrate covering the color filter, the overcoat layer having openings exposing portions of the gate line and the gate electrode, a gate insulating layer on the overcoat layer, the color filter layer, the gate line, and the gate electrode, a semiconductor layer on the gate insulating layer, wherein the semiconductor layer has a width smaller than the gate electrode, source and drain electrodes on the gate insulating layer, contacting portions of the semiconductor layer, wherein the gate electrode, the semiconductor layer, the source electrode, and the drain electrode constitute a thin film transistor, a data line on the gate insulating layer, extending from the source electrode, crossing the gate line, and defining a pixel region, a passivation layer covering the thin film transistor and the data line and having a drain contact hole exposing a portion of the drain electrode, and a pixel electrode on the passivation layer, contacting the drain electrode through the drain contact hole.


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