The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2005
Filed:
May. 31, 2002
Hideto Tomiie, Kanagawa, JP;
Toshio Terano, Kanagawa, JP;
Toshio Kobayashi, Kanagawa, JP;
Sony Corporation, Tokyo, JP;
Abstract
To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH), second conductivity type accumulation layer-forming regions (ACLa, ACL), second conductivity type regions (S/D, S/D), an insulating film (GD) and a first conductive layer (CL) formed on the inversion layer-forming region (CH). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D, S/D). The second conductive layer (WL) is connected to a word line and second conductivity type regions (S/D, S/D) are connected to bit lines (Bla, BLb).