Dynamic command buffer for a slave device on a data bus

Abstract

A slave device includes a command FIFO that stores commands for a device controller on a first-in, first-out basis to execute a read or write transaction. Commands are received from the data bus by an input register which supplies write commands to a dynamic stage register. A multiplexer couples the dynamic stage register and the input register to the command FIFO so that only the initial command of a single or multi-beat write burst is written to the command FIFO from the dynamic stage register. Consequently, separate write commands are not stored for each data beat, resulting in minimal areal size for the integrated circuit chip containing the command FIFO. Instead, a counter counts the number of beats in the multi-beat burst, so that when the last beat is received, the initial command and the beat count are supplied to the command FIFO. The device controller calculates the starting address of each subsequent data beat based on the prior beat address and the size of the data beat, to a limit established by the beat count. Non-queued read commands are transferred by the multiplexer directly from the input register to the command FIFO so that latency is not added to the processing of read commands.