Shift register and image display apparatus using the same

Abstract

A level shifteris provided for each of SR flip flops Fconstituting a shift registerThe level shifterincreases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifterand the operation is suspended at the end of the pulse output. Thus, the level shifterscan operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop FAs a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.